Efficient hardware implementations of low bit depth motion estimation algorithms

In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures

Fast inter mode decision exploiting intra-block similarity in HEVC

Video coding standards mainly aim to decrease bit-rate to be transmitted while maintaining video quality at a certain level. Mode decision used in inter- and intra-prediction stages is a vital component of video coding and is closely related to video coding efficiency and complexity. Therefore, fast and efficient mode decision algorithms are required to reduce encoding time while keeping the video quality at a certain level. In this paper, a fast inter mode decision method for HEVC is proposed. Firstly, an early selection considering intra-block similarity by making use of integral image at the prediction unit level is introduced. Secondly, a flexible early termination mode at the coding unit level is presented. The performance of the proposed method in these units is evaluated separately and together. Experimental results demonstrate the low complexity of the proposed method without any important loss in coding efficiency. The proposed method provides a good balance between coding efficiency and time savings compared to the state-of-the-art approaches

Modified phase-correlation based robust hard-cut detection with application to archive film

This paper targets hard-cut detection for archive film, i.e., mainly black-and-white videos from the beginning of the last century, which is a particularly difficult task due to heavy visual degradations encountered in the sequences. A robust hard-cut detection system based on modified phase correlation is presented. Phase-correlation-based hard-cut detection is carried out using spatially sub-sampled video frames, and a candidate hard-cut is indicated in the case of low correlation. A double thresholding approach consisting of a global threshold used in conjunction with an adaptive local threshold is used to detect candidate hard-cuts. For uniformly colored video frames the phase correlation is extremely sensitive to noise and visual defects. Mean and variance based simple heuristic false removal at uniformly colored video frames is used at the final stage to prevent false detections in such cases. The paper provides a through theoretical analysis to show the usefulness of spatial sub-sampling. Furthermore through experimental results are presented for visual defects encountered in archive film material, to present the effectiveness of the proposed approach

Shot-cut detection for B&W archive films using best-fitting kernel

A novel shot-cut detection method for black and white (B&W) archive films, employing the best-fitting kernel between two consecutive image frames is proposed in this paper. The best-fitting kernel, obtained using least squares, is used to estimate the second frame of each successive frame pair. The absolute frame difference between estimated and original image frames is utilized as criterion to decide a candidate scene-cut. A double thresholding approach, consisting of global and local adaptive thresholds, is used in this stage. Obtained candidates are forwarded to a confirmation stage to exclude single-frame defects, frequently encountered in archive film sequences. Experimental results show that the proposed method gives favorable result for B&W degraded archive films, compared to methods proposed in the literature

An all binary sub-pixel motion estimation approach and its hardware architecture

Motion estimation (ME) is the most computationally intensive part of a video coding system. Therefore it is very important to reduce its computational complexity. In this paper, a novel all-binary approach for reducing the computational complexity of sub-pixel accurate ME is proposed. An efficient hardware architecture for the proposed all-binary sub-pixel accurate motion estimation approach is also presented. The proposed hardware architecture has significantly low hardware complexity and therefore very low power consumption. It can process 720p video frames at 30 fps in a pipelined fashion together with the integer ME hardware. Therefore, it can be used in real-time low power video coding systems required by many mobile consumer electronics devices

MVBLA based design of constrained 1-bit transform based motion estimation algorithm

In this work a novel hardware proposed for Constrained 1-bit Transform based motion estimation to facilitate real time operation. The designed system occupies a small area in a general purpose FPGA fabric and it is therefore efficient to implement a whole video coding architecture on a single FPGA chip. The designed system can perform ME operation for a 2048×1152 pixel sized image frame at a speed of 20 frames/second